The present disclosure relates to semiconductor devices and manufacturing methods of the devices, and more particularly to semiconductor devices including metal insulator semiconductor field effect transistors (MISFETs) having different operating voltages and manufacturing methods of the devices.
In recent years, with higher integration, higher function, and higher speed of semiconductor integrated circuit devices, miniaturization and higher drive capability of MISFETs (hereinafter referred to as a “MIS transistor”) have been required.
On the other hand, lower power consumption of semiconductor integrated circuit devices is also required for reduction in energy consumption and for long-period use of mobile phones. Thus, reduction in operating voltages of MIS transistors for internal circuits progresses. By contrast, input/output (I/O) MIS transistor needs to be connected to external devices, and thus require higher operating voltages than MIS transistors for internal circuits.
Thus, a semiconductor device including a first, second, and third MIS transistors having different operating voltages is suggested. (See, for example, Japanese Patent Publication No. 2002-343879.) A manufacturing method of a conventional semiconductor device will be described below with reference to FIGS. 3A-3C and FIGS. 4A and 4B. FIGS. 3A-4B are cross-sectional illustrating main steps of the manufacturing method of the conventional semiconductor device in a gate length direction in order of the steps. A “first, second, and third MIS regions” shown in FIGS. 3A-4B denote regions in which first, second, and third MIS transistors are formed, respectively. The second MIS transistor has an operating voltage lower than the operating voltage of the first MIS transistor, and higher than the operating voltage of the third MIS transistor.
First, as shown in FIG. 3A, an isolation region 101 is selectively formed in an upper portion of a semiconductor substrate 100. As a result, a first, second, and third active regions 100a, 100b, and 100c surrounded by the isolation region 101 are formed in the first, second, and third MIS regions of the semiconductor substrate 100, respectively. Then, a first, second, and third channel diffusion layers 102a, 102b, and 102c are formed in upper portions of the first, second, and third active regions 100a, 100b, and 100c, respectively. After that, first thermal oxidation for forming a gate insulating film is performed to provide a first film 103 for forming a silicon oxide film on the first, second, and third active regions 100a, 100b, and 100c. 
Next, as shown in FIG. 3B, a resist pattern Re1, which covers the first and third MIS regions and exposes the second MIS region, is formed on the first film 103 for forming a silicon oxide film by photolithography. Then, the portion of the first film 103 for forming a silicon oxide film, which is provided in the second MIS region, is removed by etching using the resist pattern Re1 as a mask. This exposes a surface of a second active region 100b. After that, the resist pattern Re1 is removed.
Then, as shown in FIG. 3C, second thermal oxidation for forming a gate insulating film is performed to provide on the second active region 100b, a second film 104 for forming a silicon oxide film having a smaller thickness than the first film 103 for forming a silicon oxide film.
After that, as shown in FIG. 4A, a resist pattern Re2, which covers the first and second MIS regions and exposes the third MIS region, is formed on the first and second films 103 and 104 for forming silicon oxide films. Then, the portion of the first film 103 for forming a silicon oxide film, which is formed in the third MIS region, is removed by etching using the resist pattern Re2 as a mask. This exposes a surface of the third active region 100c. Then, the resist pattern Re2 is removed.
Next, as shown in FIG. 4B, third thermal oxidation for forming a gate insulating film is performed to provide on the third active region 100c, a third film 105 for forming a silicon oxide film having a smaller thickness than the second film 104 for forming a silicon oxide film.
Then, although not shown in the figure, a film for forming a gate electrode is formed on the first, second, and third films 103, 104, and 105 for forming silicon oxide films. After that, the film for forming a gate electrode, as well as the first, second, and third films 103, 104, and 105 for forming silicon oxide films are sequentially patterned. As a result, a first gate insulating film (not shown), which is the first film for forming a silicon oxide film, and a first gate electrode (not shown) formed of the film for forming a gate electrode are sequentially provided on the first active region 100a. A second gate insulating film (not shown), which is the second film for forming a silicon oxide film, and a second gate electrode (not shown) formed of the film for forming a gate electrode are sequentially provided on the second active region 100b. A third gate insulating film (not shown), which is the third film for forming a silicon oxide film, and a third gate electrode (not shown) formed of the film for forming a gate electrode are sequentially provided on the third active region 100c. At this time, as described above, the second film 104 for forming a silicon oxide film has a thickness smaller than the thickness of the first film 103 for forming a silicon oxide film, and greater than the thickness of the third film 105 for forming a silicon oxide film. Thus, the second gate insulating film has a thickness smaller than the thickness of the first gate insulating film and greater than the third gate insulating film.
As described above, the conventional semiconductor device is manufactured.